1. Field of the Invention
The present invention relates generally to the sequential allocation of addresses in a computer memory, and more specifically, to such an allocation which mitigates the damage resulting from hardware or software errors by reducing the possibility of relatively recent data being overwritten.
2. Description of the Prior Art
Data is stored or written in selected addresses in a digital computer's memory. When a hardware or software error occurs, data may be conveyed to an unintended memory address. If such address is already storing information, such information will be lost when it is overwritten by the misdirected data.
Addressing mechansisms route data serially to chosen locations in computer memory. Data meant for one address may be directed, as a result of computer error, to another address which is proximate the former in the sequence. This proximate but erroneously selected address may contain relatively recent information which will be corrupted by the misguided data. Such recent information may well be quite valuable, and its loss, therefore, significant.
Accordingly, there is a need for an apparatus that allocates data to a sequence of addresses such that in the event of computer error that routes data to an unintended address, more recent and therefore, generally, more valuable information will not likely be overwritten.